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? semiconductor components industries, llc, 2002 may, 2002 rev. 3 1 publication order number: mc33077/d mc33077 low noise dual operational amplifier the mc33077 is a precision high quality, high frequency, low noise monolithic dual operational amplifier employing innovative bipolar design techniques. precision matching coupled with a unique analog resistor trim technique is used to obtain low input offset voltages. dualdoublet frequency compensation techniques are used to enhance the gain bandwidth product of the amplifier. in addition, the mc33077 offers low input noise voltage, low temperature coefficient of input offset voltage, high slew rate, high ac and dc open loop voltage gain and low supply current drain. the all npn transistor output stage exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open loop output impedance and symmetrical source and sink ac frequency performance. the mc33077 is available in plastic dip and so8 packages (p and d suffixes). ? low voltage noise: 4.4 nv/ hz @ 1.0 khz ? low input offset voltage: 0.2 mv ? low tc of input offset voltage: 2.0 v/ c ? high gain bandwidth product: 37 mhz @ 100 khz ? high ac voltage gain: 370 @ 100 khz 1850 @ 20 khz ? unity gain stable: with capacitance loads to 500 pf ? high slew rate: 11 v/ s ? low total harmonic distortion: 0.007% ? large output voltage swing: +14 v to 14.7 v ? high dc open loop voltage gain: 400 k (112 db) ? high common mode rejection: 107 db ? low power supply drain current: 3.5 ma ? dual supply operation: 2.5 v to 18 v device package shipping ordering information mc33077d so8 98 units/rail mc33077dr2 so8 2500 tape & reel pdip8 p suffix case 626 1 8 so8 d suffix case 751 1 8 marking diagrams 1 8 1 8 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week mc33077p pdip8 50 units/rail pin connections 4 2 v ee 1 3 5 6 7 8v cc output 2 inputs 2 inputs 1 (dual, top view) - + 1 - + 2 output 1 33077 alyw mc33077p awl yyww http://onsemi.com
mc33077 http://onsemi.com 2 q1 r1 r6 r8 r11 r16 q17 q19 q13 q11 d3 r9 c3 q8 r3 q6 c1 j 1 q1 d 1 q5 r2 r4 r7 r5 c2 pos q7 q9 q10 q12 v cc q21 v out r19 q22 r20 q20 c8 c7 d7 r17 r18 d6 q14 d4 r13 c6 r14 q16 z1 neg q4 d2 r10 r12 d5 r15 v ee bias network figure 1. representative schematic diagram (each amplifier) q2
mc33077 http://onsemi.com 3 maximum ratings rating symbol value unit supply voltage (v cc to v ee ) v s +36 v input differential voltage range v idr note 1 v input voltage range v ir note 1 v output short circuit duration (note 2) t sc indefinite sec maximum junction temperature t j +150 c storage temperature t stg 60 to +150 c maximum power dissipation p d note 2 mw operating temperature range t a 40 to + 85 c dc electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit input offset voltage (r s = 10 , v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c |v io | 0.13 1.0 1.5 mv average temperature coefficient of input offset voltage r s = 10 , v cm = 0 v, v o = 0 v, t a = 40 to +85 c v io / t 2.0 v/ c input bias current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c i ib 280 1000 1200 na input offset current (v cm = 0 v, v o = 0 v) t a = +25 c t a = 40 to +85 c i io 15 180 240 na common mode input voltage range ( v io ,= 5.0 mv, v o = 0 v) v icr 13.5 14 v large signal voltage gain (v o = 1.0 v, r l = 2.0 k ) t a = +25 c t a = 40 to +85 c a vol 150 125 400 kv/v output voltage swing (v id = 1.0 v) r l = 2.0 k r l = 2.0 k r l = 10 k r l = 10 k v o+ v o v o+ v o +13.0 +13.4 +13.6 14.1 +14.0 14.7 13.5 14.3 v common mode rejection (v in = 13 v) cmr 85 107 db power supply rejection (note 3) v cc /v ee = +15 v/ 15 v to +5.0 v/ 5.0 v psr 80 90 db output short circuit current (v id = 1.0 v, output to ground) source sink i sc +10 20 +26 33 +60 +60 ma power supply current (v o = 0 v, all amplifiers) t a = +25 c t a = 40 to +85 c i d 3.5 4.5 4.8 ma 1. either or both input voltages should not exceed v cc or v ee (see applications information). 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded (see power dissipation performance characteristic, figure 2). 3. measured with v cc and v ee simultaneously varied.
mc33077 http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit slew rate (v in = 10 v to +10 v, r l = 2.0 k , c l = 100 pf, a v = +1.0) sr 8.0 11 v/ s gain bandwidth product (f = 100 khz) gbw 25 37 mhz ac voltage gain (r l = 2.0 k , v o = 0 v) f = 100 khz f = 20 khz a vo 370 1850 v/v unity gain bandwidth (open loop) bw 7.5 mhz gain margin (r l = 2.0 k , c l = 10 pf) a m 10 db phase margin (r l = 2.0 k , c l = 10 pf) ? m 55 deg channel separation (f = 20 hz to 20 khz, r l = 2.0 k , v o = 10 v pp ) cs 120 db power bandwidth (v o = 27 pp , r l = 2.0 k , thd 1%) bw p 200 khz distortion (r l = 2.0 k a v = +1.0, f = 20 hz to 20 khz v o = 3.0 v rms a v = 2000, f = 20 khz v o = 2.0 v pp v o = 10 v pp a v = 4000, f = 100 khz v o = 2.0 v pp v o = 10 v pp thd 0.007 0.215 0.242 0.3.19 0.316 % open loop output impedance (v o = 0 v, f = f u ) |z o | 36 differential input resistance (v cm = 0 v) r in 270 k differential input capacitance (v cm = 0 v) c in 15 pf equivalent input noise voltage (r s = 100 ) f = 10 hz f = 1.0 khz e n 6.7 4.4 nv/ hz equivalent input noise current (f = 1.0 khz) f = 10 hz f = 1.0 khz i n 1.3 0.6 pa/ hz p d(max) , maximum power dissipation (mw) figure 2. maximum power dissipation versus temperature figure 3. input bias current versus supply voltage t a , ambient temperature ( c) mc33077p mc33077d v cc , |v ee |, supply voltage (v) , input bias current (na) i ib v cm = 0 v t a = 25 c 2400 2000 1600 1200 800 400 0 800 600 400 200 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0 2.5 5.0 7.5 10 12.5 15 17.5 20
mc33077 http://onsemi.com 5 figure 4. input bias current versus temperature figure 5. input offset voltage versus temperature figure 6. input bias current versus common mode voltage figure 7. input common mode voltage range versus temperature figure 8. output saturation voltage versus load resistance to ground figure 9. output short circuit current versus temperature t a , ambient temperature ( c) v cc = +15 v v ee = -15 v v cm = 0 v , input bias current (na) i ib v, input offset voltage (mv) io t a , ambient temperature ( c) v cc = +15 v v ee = -15 v r s = 10 v cm = 0 v a v = +1.0 v cm , common mode voltage (v) , input bias current (na) i ib v cc = +15 v v ee = -15 v t a = 25 c t a , ambient temperature ( c) input voltage range v cc = +3.0 v to +15 v v ee = -3.0 v to -15 v v io = 5.0 mv v o = 0 v +v cm -v cm v icr , input common mode votage range (v) r l , load resistance to ground (k ) v , output saturation voltage (v) sat v cc = +15 v v ee = -15 v 125 c 25 c -55 c 125 c 25 c -55 c sink source t a , ambient temperature ( c) |i|, output short circuit current (ma) sc v cc = +15 v v ee = -15 v v id = 1.0 v r l < 100 1000 800 600 400 200 0 1.0 0.5 0 -0.5 -1.0 600 500 400 300 200 100 0 v cc 0.0 v cc -0.5 v cc -1.0 v cc -1.5 v ee +1.5 v ee +1.0 v ee +0.5 v ee +0.0 v cc 0 v cc -2 v cc -4 v ee +4 v ee +2 v ee 0 50 40 30 20 10 -55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125 -15 -10 -5.0 0 5.0 10 15 -55 -25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 -55 -25 0 25 50 75 100 125
mc33077 http://onsemi.com 6 figure 10. supply current versus temperature figure 11. common mode rejection versus frequency figure 12. power supply rejection versus frequency figure 13. gain bandwidth product versus supply voltage figure 14. gain bandwidth product versus temperature figure 15. maximum output voltage versus supply voltage 15 v i, supply current (ma) cc t a , ambient temperature ( c) 5.0 v v cm = 0 v r l = v o = 0 v cmr, common mode rejection (db) f, frequency (hz) v cc = +15 v v ee = -15 v v cm = 0 v v cm = 1.5 v t a = 25 c f, frequency (hz) psr, power supply rejection (db) -psr +psr +psr = 20log v o /a dm v cc -psr = 20log v o /a dm v ee r l = 10 k c l = 0 pf f = 100 khz t a = 25 c gbw, gain bandwidth product (mhz) v cc , |v ee |, supply voltage (v) t a , ambient temperature ( c) gbw, gain bandwidth product (mhz) v cc = +15 v v ee = -15 v f = 100 khz r l = 10 k c l = 0 pf v p + v p - v cc , |v ee |, supply voltage (v) v o ,output voltage (v ) p r l = 10 k r l = 10 k r l = 2.0 k r l = 2.0 k t a = 25 c 5.0 4.0 3.0 2.0 1.0 0 120 100 80 60 40 20 0 120 100 80 60 40 20 0 48 44 40 36 32 28 24 50 46 42 38 34 30 26 20 15 10 5.0 0 -5.0 -10 -15 -20 -55 -25 0 25 50 75 100 125 100 1.0 k 10 k 100 k 1.0 m 10 m 100 1.0 k 10 k 100 k 1.0 m 0 5 10 15 20 -55 -25 0 25 50 75 100 125 0 5.0 10 15 20 cmr = 20log - + a dm v cm v o v o v cm a dm v cc = +15 v v ee = -15 v t a = 25 c - + v o a dm v ee v cc
mc33077 http://onsemi.com 7 v o , output voltage (v ) pp figure 16. output voltage versus frequency figure 17. open loop voltage gain versus supply voltage figure 18. open loop voltage gain versus temperature figure 19. output impedance versus frequency figure 20. channel separation versus frequency figure 21. total harmonic distortion versus frequency f, frequency (hz) v cc , |v ee |, supply voltage (v) open loop voltage gain (x1000 v/v) a vol , r l = 2.0 k f = 10 hz v o = 2/3 (v cc -v ee ) t a = 25 c open loop voltage gain (x1000 v/v) a vol , t a , ambient temperature ( c) v cc = +15 v v ee = -15 v r l = 2.0 k f = 10 hz v o = -10 v to +10 v f, frequency (hz) cs, channel separation (db) v od v in cs = 20 log drive channel v cc = +15 v v ee = -15 v r l = 2.0 k v od = 20 v pp t a = 25 c a v = +10 a v = +100 a v = +1000 thd, total harmonic distortion (%) f, frequency (hz) a v = 1000 a v = 100 a v = 10 a v = 1.0 f, frequency (hz) | z|, output impedance () o w 30 25 20 15 10 5.0 0 1200 1000 800 600 400 200 0 600 550 500 450 400 350 300 160 150 140 130 120 110 100 1.0 0.1 0.01 0.001 80 70 60 50 40 30 20 10 0 100 1.0 k 10 k 100 k 1.0 m 0 5.0 10 15 20 -55 -25 0 25 50 75 100 125 10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k 100 1.0 k 10 k 100 k 1.0 m 10 m v cc = +15 v v ee = -15 v r l = 2.0 k a v =+1.0 thd 1.0% t a = 25 c v cc = +15 v v ee = -15 v v o = 0 v t a = 25 c v in v o - + measurement channel v cc = +15 v v o = 2.0 vpp v ee = -15 v t a = 25 c v in v o - + 2.0k r a 100k a v = +1.0
mc33077 http://onsemi.com 8 a v = +1000 a v = +100 a v = +10 a v = +1.0 figure 22. total harmonic distortion versus frequency figure 23. total harmonic distortion versus output voltage figure 24. slew rate versus supply voltage figure 25. slew rate versus temperature figure 26. voltage gain and phase versus frequency figure 27. open loop gain margin and phase margin versus output load capacitance v cc = +15 v v ee = -15 v v 0 = -10 vpp t a = 25 c thd, total harmonic distortion (%) f, frequency (hz) v o , output voltage (v pp ) thd, total harmonic distortion (%) v cc = +15 v v ee = -15 v f = 20 khz t a = 25 c v cc , |v ee |, supply voltage (v) sr, slew rate (v/s) m v in = 2/3 (v cc -v ee ) t a = 25 c sr, slew rate (v/ s) m t a , ambient temperature ( c) v cc = +15 v v ee = -15 v v in = 20 v f, frequency (hz) 0 40 80 120 160 200 240 f , excess phase (degrees) open-loop voltage gain (db) a vol , a, open loop gain margin (db) m 0 10 20 30 40 50 60 f , phase margin (degrees) m 70 c l , output load capacitance (pf) v cc = +15 v v ee = -15 v v o = 0 v phase gain 125 c 25 c -55 c -55 c 25 c 125 c gain phase v cc = +15 v v ee = -15 v r l = 2.0 k t a = 25 c 1.0 0.1 0.01 0.001 1.0 0.5 0.1 0.05 0.01 0.005 0.001 16 12 8.0 4.0 0 40 30 20 10 0 180 140 100 60 20 -20 -60 14 12 10 8.0 6.0 4.0 2.0 0 10 100 1.0 k 10 k 100 k 0 2.0 4.0 6.0 8.0 10 12 0 2.5 5.0 7.5 10 12.5 15 17.5 20 -25 0 25 50 75 100 125 -55 10 100 1.0 k 10 k 100 k 1.0 m 10 m 100 m 1.0 10 100 1000 v in v o - + 2.0k r a 100k a v = +1000 a v = +100 a v = +10 a v = +1.0 v in v o - + 2.0k r a 100k v in v o 100pf 2.0k - + vo 100pf 2.0k - + v in v in v o c l 2.0k - +
mc33077 http://onsemi.com 9 v cc = +15 v v ee = -15 v r t = r 1 + r 2 v o = 0 v t a = 25 c gain phase 125 c and 25 c -55 c v cc = +15 v v ee = -15 v v in = 100 mv figure 28. phase margin versus output voltage figure 29. overshoot versus output load capacitance figure 30. input referred noise voltage and current versus frequency figure 31. total input referred noise voltage versus source resistant figure 32. phase margin and gain margin versus differential source resistance figure 33. inverting amplifer slew rate v o , output voltage (v) v cc = +15 v v ee = -15 v t a = 25 c c l = 0 pf c l = 100 pf c l = 300 pf c l = 500 pf f , phase margin (degrees) m c l , output load capacitance (pf) os, overshoot (%) f, frequency (hz) e, input referred noise voltage ( ) n 10 5.0 3.0 2.0 1.0 0.5 0.3 0.2 0.1 i,input referred noise current (pa) n nv/ hz v, total referred noise voltage ( ) n v cc = +15 v f = 1.0 khz v ee = -15 v t a = 25 c v n (total) = r s , source resistance ( ) nv/ hz 0 10 20 30 40 50 60 70 f m ,phase margin (degrees) r t , differential source resistance ( ) a, gain margin (db) m v, output voltage (5.0 v/div) o t, time (2.0 s/div) v 70 60 50 40 30 20 10 0 100 80 60 40 20 0 100 50 30 20 10 5.0 3.0 2.0 1.0 1000 100 10 1.0 14 12 10 8.0 6.0 4.0 2.0 0 -10 -5.0 0 5.0 10 1 10 100 1000 1.0 10 100 1.0 k 10 k 100 k 10 100 1.0 k 10 k 100 k 1.0 m 1.0 10 100 1.0 k 10 k v in v o c l 2.0k - + v o 100pf 2.0k - + v in v cc = +15 v v ee = -15 v t a = 25 c voltage current r2 v o - + v in r1 (i n r s ) 2 e n 2 4ktr s v cc = +15 v v ee = -15 v a v = -1.0 r l = 2.0 k c l = 100 pf t a = 25 c
mc33077 http://onsemi.com 10 figure 34. noninverting amplifier slew rate figure 35. noninverting amplifier overshoot figure 36. low frequency noise voltage versus time v , output voltage (5.0 v/div) o t, time (2.0 s/div) t, time (200 ns/div) e , input noise voltage (100nv/div) n t, time (1.0 sec/div) v , output voltage (5.0 v/div) o v cc = +15 v v ee = -15 v a v = +1.0 r l = 2.0 k t a = 25 c c l = 0 pf c l = 100 pf v cc = +15 v v ee = -15 v bw = 0.1 hz to 10 hz t a = 25 c see noise circuit (figure 36) v cc = +15 v v ee = -15 v a v = +1.0 r l = 2.0 k c l = 100 pf t a = 25 c
mc33077 http://onsemi.com 11 applications information the mc33077 is designed primarily for its low noise, low offset voltage, high gain bandwidth product and large output swing characteristics. its outstanding high frequency gain/phase performance make it a very attractive amplifier for high quality preamps, instrumentation amps, active filters and other applications requiring precision quality characteristics. the mc33077 utilizes high frequency lateral pnp input transistors in a low noise bipolar differential stage driving a compensated miller integration amplifier. dualdoublet frequency compensation techniques are used to enhance the gain bandwidth product. the output stage uses an all npn transistor design which provides greater output voltage swing and improved frequency performance over more conventional stages by using both pnp and npn transistors (class ab). this combination produces an amplifier with superior characteristics. through precision component matching and innovative current mirror design, a lower than normal temperature coefficient of input offset voltage (2.0 v/ c as opposed to 10 v/ c), as well as low input offset voltage, is accomplished. the minimum common mode input range is from 1.5 v below the positive rail (v cc ) to 1.5 v above the negative rail (v ee ). the inputs will typically common mode to within 1.0 v of both negative and positive rails though degradation in offset voltage and gain will be experienced as the common mode voltage nears either supply rail. in practice, though not recommended, the input voltage may exceed v cc by approximately 3.0 v and decrease below the v ee by approximately 0.6 v without causing permanent damage to the device. if the input voltage on either or both inputs is less than approximately 0.6 v, excessive current may flow, if not limited, causing permanent damage to the device. the amplifier will not latch with input source currents up to 20 ma, though in practice, source currents should be limited to 5.0 ma to avoid any parametric damage to the device. if both inputs exceed v cc , the output will be in the high state and phase reversal may occur. no phase reversal will occur if the voltage on one input is within the common mode range and the voltage on the other input exceeds v cc . phase reversal may occur if the input voltage on either or both inputs is less than 1.0 v above the negative rail. phase reversal will be experienced if the voltage on either or both inputs is less than v ee . through the use of dualdoublet frequency compensation techniques, the gain bandwidth product has been greatly enhanced over other amplifiers using the conventional single pole compensation. the phase and gain error of the amplifier remains low to higher frequencies for fixed amplifier gain configurations. with the all npn output stage, there is minimal swing loss to the supply rails, producing superior output swing, no crossover distortion and improved output phase symmetry with output voltage excursions (output phase symmetry being the amplifiers ability to maintain a constant phase relation independent of its output voltage swing). output phase symmetry degradation in the more conventional pnp and npn transistor output stage was primarily due to the inherent cutoff frequency mismatch of the pnp and npn transistors used (typically 10 mhz and 300 mhz, respectively), causing considerable phase change to occur as the output voltage changes. by eliminating the pnp in the output, such phase change has been avoided and a very significant improvement in output phase symmetry as well as output swing has been accomplished. the output swing improvement is most noticeable when operation is with lower supply voltages (typically 30% with 5.0 v supplies). with a 10 k load, the output of the amplifier can typically swing to within 1.0 v of the positive rail (v cc ), and to within 0.3 v of the negative rail (v ee ), producing a 28.7 v pp signal from 15 v supplies. output voltage swing can be further improved by using an output pullup resistor referenced to the v cc . where output signals are referenced to the positive supply rail, the pullup resistor will pull the output to v cc during the positive swing, and during the negative swing, the npn output transistor collector will pull the output very near v ee . this configuration will produce the maximum attainable output signal from given supply voltages. the value of load resistance used should be much less than any feedback resistance to avoid excess loading and allow easy pullup of the output. output impedance of the amplifier is typically less than 50 at frequencies less than the unity gain crossover frequency (see figure 19). the amplifier is unity gain stable with output capacitance loads up to 500 pf at full output swing over the 55 to +125 c temperature range. output phase symmetry is excellent with typically 4 c total phase change over a 20 v output excursion at 25 c with a 2.0 k and 100 pf load. with a 2.0 k resistive load and no capacitance loading, the total phase change is approximately one degree for the same 20 v output excursion. with a 2.0 k and 500 pf load at 125 c, the total phase change is typically only 10 c for a 20 v output excursion (see figure 28). as with all amplifiers, care should be exercised to insure that one does not create a pole at the input of the amplifier which is near the closed loop corner frequency. this becomes a greater concern when using high frequency amplifiers since it is very easy to create such a pole with relatively small values of resistance on the inputs. if this does occur, the amplifier's phase will degrade severely causing the amplifier to become unstable. effective source resistances, acting in conjunction with the input capacitance of the amplifier, should be kept to a minimum to avoid creating such a pole at the input (see figure 32). there is minimal effect on stability where the created input pole is much greater than the closed loop corner frequency. where amplifier stability is affected as a result of a negative feedback resistor in conjunction with the
mc33077 http://onsemi.com 12 amplifier's input capacitance, creating a pole near the closed loop corner frequency, lead capacitor compensation techniques (lead capacitor in parallel with the feedback resistor) can be employed to improve stability. the feedback resistor and lead capacitor rc time constant should be larger than that of the uncompensated input pole frequency. having a high resistance connected to the noninverting input of the amplifier can create a like instability problem. compensation for this condition can be accomplished by adding a lead capacitor in parallel with the noninverting input resistor of such a value as to make the rc time constant larger than the rc time constant of the uncompensated input resistor acting in conjunction with the amplifiers input capacitance. for optimum frequency performance and stability, careful component placement and printed circuit board layout should be exercised. for example, long unshielded input or output leads may result in unwanted input output coupling. in order to reduce the input capacitance, the body of resistors connected to the input pins should be physically close to the input pins. this not only minimizes the input pole creation for optimum frequency response, but also minimizes extraneous signal apickupo at this node. power supplies should be decoupled with adequate capacitance as close as possible to the device supply pin. in addition to amplifier stability considerations, input source resistance values should be low to take full advantage of the low noise characteristics of the amplifier. thermal noise (johnson noise) of a resistor is generated by thermallycharged carriers randomly moving within the resistor creating a voltage. the rms thermal noise voltage in a resistor can be calculated from: e nr = 4k tr bw / where: k = boltzmann's constant (1.38 10 23 joules/k) t = kelvin temperature r = resistance in ohms bw = upper and lower frequency limit in hertz. by way of reference, a 1.0 k resistor at 25 c will produce a 4.0 nv/ hz of rms noise voltage. if this resistor is connected to the input of the amplifier, the noise voltage will be gainedup in accordance to the amplifier's gain configuration. for this reason, the selection of input source resistance for low noise circuit applications warrants serious consideration. the total noise of the amplifier, as referred to its inputs, is typically only 4.4 nv/ hz at 1.0 khz. the output of any one amplifier is current limited and thus protected from a direct short to ground, however, under such conditions, it is important not to allow the amplifier to exceed the maximum junction temperature rating. typically for 15 v supplies, any one output can be shorted continuously to ground without exceeding the temperature rating. figure 37. voltage noise test circuit (0.1 hz to 10 hz pp ) note: all capacitors are nonpolarized. + - 0.1 f 10 100 k 2.0 k 4.7 f voltage gain = 50,000 scope 1 r in = 1.0 m 1/2 mc33077 - + d.u.t. 100 k 0.1 f 2.2 f 22 f 24.3 k 4.3 k 110 k
mc33077 http://onsemi.com 13 package dimensions pdip8 p suffix case 62605 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 so8 d suffix case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc33077 http://onsemi.com 14 notes
mc33077 http://onsemi.com 15 notes
mc33077 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33077/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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